My reworking of the Verilog code for the Go Board from Nandland.com and Getting Started with FPGAs (https://github.com/nandland/getting-started-with-fpgas/)
John Bintz
11cea6b1cf
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| .gitignore | ||
| Go_Board_Constraints.pcf | ||
| Makefile | ||
| README.md | ||
| binary_to_7_segment.v | ||
| build_image.rb | ||
| count_and_toggle.v | ||
| debounce_filter.v | ||
| debounce_project_top.v | ||
| demux_1_to_4.v | ||
| double_dabble.rb | ||
| double_dabble_counters.bin | ||
| double_dabble_counters.v | ||
| fifo.v | ||
| image_data.txt | ||
| image_index_to_color.v | ||
| image_ram.v | ||
| image_ram_dat.txt | ||
| led_toggle.v | ||
| lfsr_22.v | ||
| palette_data.txt | ||
| pong.v | ||
| pong_ball.v | ||
| pong_paddle.v | ||
| pong_runner.bin | ||
| pong_runner.v | ||
| ram.v | ||
| simon.v | ||
| simon_game.v | ||
| sipo_shift_register_test.sv | ||
| uart_rx.v | ||
| uart_tx.v | ||
| vga_add_porches_to_output.v | ||
| vga_current_beam_position.v | ||
| vga_image_renderer.bin | ||
| vga_image_renderer.v | ||
| vga_image_renderer_top.bin | ||
| vga_image_renderer_top.v | ||
| vga_pattern_generator.v | ||
| vga_sync_pulse_generator.v | ||
| vga_tester.v | ||
README.md
Go Board code reworking
This code is a reworking of the code for the Go Board FPGA beginner's board.
The original code comes from two sources:
Where possible I tried to:
- use more consistent variable and constant names
- fix missing inferred wires (the Pong project had a lot of these)
- avoid run-on lines of code
- avoid one-liner conditional bodies, opting for
begin...endblocks everywhere
All of these can be built with Yosys
and tested with Icarus Verilog. The Makefile is one I've been dragging along across all projects. It can fire off both a build-and-install to the Go Board, as well as run the test suite and open up GTKWave
so you can inspect the signals. You do not need Lattice iCECube2 or have to jump through their
licensing hoops, and you will have a hard time getting it to run on modern Linux anyway!
sipo_shift_register_test.sv shows how to create your own assert for Icarus Verilog,
taken from an idea from here: https://stackoverflow.com/a/13906120
Have fun.
John