19 lines
363 B
Verilog
19 lines
363 B
Verilog
module LFSR(
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input i_Clk,
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output [SIZE-1:0] o_LFSR_Data,
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output o_LFSR_Done
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);
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parameter SIZE = 22;
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reg [SIZE-1:0] r_LFSR;
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wire w_XNOR;
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always @(posedge i_Clk) begin
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r_LFSR <= {r_LFSR[SIZE-2:0], w_XNOR};
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end
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assign w_XNOR = r_LFSR[SIZE-1] ^~ r_LFSR[SIZE-2];
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assign o_LFSR_Done = (r_LFSR == 0);
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assign o_LFSR_Data = r_LFSR;
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endmodule
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