93 lines
1.5 KiB
Verilog
93 lines
1.5 KiB
Verilog
module ImageRAM(
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input i_Clk,
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input i_doRead,
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input [$clog2(WIDTH)-1:0] i_ReadX,
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input [$clog2(HEIGHT)-1:0] i_ReadY,
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input [$clog2(WIDTH)-1:0] i_WriteX,
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input [$clog2(HEIGHT)-1:0] i_WriteY,
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input [$clog2(INDEXES)-1:0] i_WriteData,
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input i_DoWrite,
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output reg o_ReadDataReady,
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output reg [4:0] o_ReadData,
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output reg o_WriteComplete
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);
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parameter INDEXES = 8;
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parameter WIDTH = 80;
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parameter HEIGHT = 60;
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reg [4:0] r_Memory[0:HEIGHT-1][0:WIDTH-1];
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initial begin
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$readmemb("image_data.txt", r_Memory);
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end
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// reading
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always @(posedge i_Clk) begin
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o_ReadData <= r_Memory[i_ReadY][i_ReadX];
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o_ReadDataReady <= i_doRead;
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end
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// writing
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always @(posedge i_Clk) begin
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if (i_DoWrite) begin
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r_Memory[i_WriteY][i_WriteX] <= i_WriteData;
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o_WriteComplete <= i_DoWrite;
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end
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end
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endmodule
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module TestImageRAM();
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reg r_Clk = 0;
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always #2 r_Clk <= !r_Clk;
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reg r_doRead = 0;
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reg [5:0] r_readX = 0;
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reg [4:0] r_readY = 0;
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wire w_readDataReady;
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wire [2:0] w_readData;
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ImageRAM MyRam (
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.i_Clk(r_Clk),
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.i_doRead(r_doRead),
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.i_ReadX(r_readX),
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.i_ReadY(r_readY),
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.o_ReadDataReady(w_readDataReady),
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.o_ReadData(w_readData)
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);
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initial begin
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$dumpfile("test.vcd");
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$dumpvars;
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#2;
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#2;
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r_doRead <= 1;
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#2;
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#2;
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r_doRead <= 0;
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r_readX <= 1;
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r_readY <= 0;
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#2;
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#2;
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r_doRead <= 1;
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#2;
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#2;
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r_doRead <= 0;
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$finish;
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end
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endmodule
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