tweak readme
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@ -17,8 +17,8 @@ Where possible I tried to:
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All of these can be built with [Yosys](https://github.com/YosysHQ/yosys)
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All of these can be built with [Yosys](https://github.com/YosysHQ/yosys)
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and tested with [Icarus Verilog](https://github.com/steveicarus/iverilog). The `Makefile` is one I've been dragging along across all projects. It can fire off both a build-and-install to the Go Board, as well as run the test suite and open up [GTKWave](https://gtkwave.sourceforge.net/)
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and tested with [Icarus Verilog](https://github.com/steveicarus/iverilog). The `Makefile` is one I've been dragging along across all projects. It can fire off both a build-and-install to the Go Board, as well as run the test suite and open up [GTKWave](https://gtkwave.sourceforge.net/)
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so you can inspect the signals. You do not need Lattive iCECube2 and you will have a hard time
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so you can inspect the signals. You do not need Lattice iCECube2 or jump therough their
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getting it to run on modern Linux anyway!
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licensing hoops, and you will have a hard time getting it to run on modern Linux anyway!
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`sipo_shift_register_test.sv` shows how to create your own `assert` for Icarus Verilog,
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`sipo_shift_register_test.sv` shows how to create your own `assert` for Icarus Verilog,
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taken from an idea from here: https://stackoverflow.com/a/13906120
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taken from an idea from here: https://stackoverflow.com/a/13906120
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