From 1a86c7f5165fe5031c229c32d09e12dd93ba5c38 Mon Sep 17 00:00:00 2001 From: John Bintz Date: Sat, 6 Jul 2024 14:52:30 -0400 Subject: [PATCH] tweak readme --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 7e4a5b4..5ee38ad 100644 --- a/README.md +++ b/README.md @@ -17,8 +17,8 @@ Where possible I tried to: All of these can be built with [Yosys](https://github.com/YosysHQ/yosys) and tested with [Icarus Verilog](https://github.com/steveicarus/iverilog). The `Makefile` is one I've been dragging along across all projects. It can fire off both a build-and-install to the Go Board, as well as run the test suite and open up [GTKWave](https://gtkwave.sourceforge.net/) -so you can inspect the signals. You do not need Lattive iCECube2 and you will have a hard time -getting it to run on modern Linux anyway! +so you can inspect the signals. You do not need Lattice iCECube2 or jump therough their +licensing hoops, and you will have a hard time getting it to run on modern Linux anyway! `sipo_shift_register_test.sv` shows how to create your own `assert` for Icarus Verilog, taken from an idea from here: https://stackoverflow.com/a/13906120