34 lines
586 B
Verilog
34 lines
586 B
Verilog
module blink(
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input clk_25mhz,
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output [7:0] led,
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output wifi_gpio0
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);
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wire i_clk = clk_25mhz;
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wire [7:0] o_led = led;
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assign wifi_gpio0 = 1'b1;
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reg [$clog2(10000000)-1:0] r_counter;
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reg r_ledState = 0;
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always @(posedge i_clk) begin
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if (r_counter == 10000000) begin
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r_ledState <= !r_ledState;
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r_counter <= 0;
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end else begin
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r_counter <= r_counter + 1;
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end
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end
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assign o_led[0] = 0;
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assign o_led[1] = r_ledState;
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genvar i;
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generate
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for (i = 2; i < 8; i = i + 1) begin
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assign o_led[i] = 0;
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end
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endgenerate
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endmodule
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