35 lines
870 B
Verilog
35 lines
870 B
Verilog
// Remember, this "magically works" on the Go Board.
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// If you're using a different clock speed, you need to
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// do a different thing here.
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module VGA_Sync_Pulse_Generator (
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input i_Clk,
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output o_HSync,
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output o_VSync,
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output reg [$clog2(TOTAL_COLUMNS)-1:0] o_rawX,
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output reg [$clog2(TOTAL_ROWS)-1:0] o_rawY
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);
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// remember overscan
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parameter ACTIVE_COLUMNS = 640;
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parameter ACTIVE_ROWS = 480;
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parameter TOTAL_COLUMNS = 800;
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parameter TOTAL_ROWS = 525;
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always @(posedge i_Clk) begin
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if (o_rawX == TOTAL_COLUMNS - 1) begin
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o_rawX <= 0;
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if (o_rawY == TOTAL_ROWS - 1) begin
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o_rawY <= 0;
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end else begin
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o_rawY <= o_rawY + 1;
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end
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end else begin
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o_rawX <= o_rawX + 1;
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end
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end
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assign o_HSync = (o_rawX < ACTIVE_COLUMNS) ? 1 : 0;
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assign o_VSync = (o_rawY < ACTIVE_ROWS) ? 1 : 0;
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endmodule
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