78 lines
1.4 KiB
Verilog
78 lines
1.4 KiB
Verilog
module RAM(
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input i_writeClock,
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input [$clog2(DEPTH_WORDS - 1):0] i_writeAddress,
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input [WIDTH_BITS-1:0] i_writeData,
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input i_writeDataValid,
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input i_readClock,
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input [$clog2(DEPTH_WORDS - 1):0] i_readAddress,
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input i_doRead,
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output reg o_dataValid,
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output reg [WIDTH_BITS-1:0] o_readData
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);
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parameter WIDTH_BITS = 8;
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parameter DEPTH_WORDS = 16;
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reg [WIDTH_BITS-1:0] r_Memory[DEPTH_WORDS-1:0];
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always @(posedge i_writeClock) begin
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if (i_writeDataValid) begin
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r_Memory[i_writeAddress] <= i_writeData;
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end
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end
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always @(posedge i_readClock) begin
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o_readData <= r_Memory[i_readAddress];
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o_dataValid <= i_doRead;
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end
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endmodule
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module TestRAM();
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reg r_Clk = 0;
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always #2 r_Clk <= !r_Clk;
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reg [4:0] r_writeAddress = 1;
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reg [7:0] r_writeData = 50;
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reg r_writeDataValid = 0;
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reg [4:0] r_readAddress = 1;
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wire [7:0] w_readData;
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reg r_doRead = 0;
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wire w_dataValid;
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RAM myRam (
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.i_writeClock(r_Clk),
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.i_writeAddress(r_writeAddress),
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.i_writeData(r_writeData),
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.i_writeDataValid(r_writeDataValid),
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.i_readClock(r_Clk),
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.i_readAddress(r_readAddress),
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.i_doRead(r_doRead),
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.o_dataValid(w_dataValid),
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.o_readData(w_readData)
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);
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initial begin
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$dumpfile("test.vcd");
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$dumpvars;
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#2;
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r_writeDataValid <= 1;
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#2;
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r_writeDataValid <= 0;
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#2;
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r_doRead <= 1;
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#2;
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$finish;
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end
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endmodule
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