31 lines
499 B
Verilog
31 lines
499 B
Verilog
module Debounce_Filter
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#(parameter DEBOUNCE_LIMIT = 20) (
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input i_Clk,
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input i_Bouncy,
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output o_Debounced
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);
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reg [$clog2(DEBOUNCE_LIMIT)-1:0] r_Count = 0;
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reg r_State = 1'b0;
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always @(posedge i_Clk)
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begin
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if (i_Bouncy !== r_State && r_Count < DEBOUNCE_LIMIT - 1)
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begin
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r_Count <= r_Count + 1;
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end
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else if (r_Count == DEBOUNCE_LIMIT - 1)
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begin
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r_State <= i_Bouncy;
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r_Count <= 0;
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end
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else
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begin
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r_Count <= 0;
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end
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end
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assign o_Debounced = r_State;
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endmodule
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