105 lines
1.9 KiB
Systemverilog
105 lines
1.9 KiB
Systemverilog
module SiPo_ShiftRegister_4(
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input i_Clk,
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input i_Latch,
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input i_Data,
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input i_Reset,
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output o_Data0,
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output o_Data1,
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output o_Data2,
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output o_Data3
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);
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reg [3:0] r_Data;
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reg [3:0] r_Incoming;
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reg [2:0] r_Pos;
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reg r_didLatch;
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always @ (posedge i_Clk & i_Reset) begin
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r_Data <= 0;
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r_Incoming <= 0;
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r_Pos <= 0;
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r_didLatch <= 0;
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end
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always @ (posedge i_Clk) begin
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if (i_Latch & !r_didLatch) begin
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r_Incoming[0] <= i_Data;
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r_Incoming[3:1] <= r_Incoming[2:0];
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r_Pos <= r_Pos + 1;
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r_didLatch <= 1;
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end
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if (r_didLatch & !i_Latch) begin
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r_didLatch <= 0;
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if (r_Pos == 4) begin
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r_Data[3:0] <= r_Incoming[3:0];
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r_Incoming <= 0;
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r_Pos <= 0;
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end
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end
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end
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assign o_Data0 = r_Data[0];
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assign o_Data1 = r_Data[1];
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assign o_Data2 = r_Data[2];
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assign o_Data3 = r_Data[3];
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endmodule
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module Test_SIPO();
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task assert(input condition);
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if (!condition) $error;
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endtask
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reg r_Data = 1'b0, r_Clk = 1'b0, r_Latch = 1'b0, r_Reset = 1'b0;
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wire w_Data0, w_Data1, w_Data2, w_Data3;
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always #2 r_Clk <= !r_Clk;
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SiPo_ShiftRegister_4 UUT(
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.i_Clk(r_Clk),
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.i_Data(r_Data),
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.i_Latch(r_Latch),
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.i_Reset(r_Reset),
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.o_Data0(w_Data0),
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.o_Data1(w_Data1),
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.o_Data2(w_Data2),
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.o_Data3(w_Data3)
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);
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initial begin
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$dumpfile("test.vcd");
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$dumpvars;
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r_Data <= 1'b1;
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r_Reset <= 1'b1;
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@(posedge r_Clk);
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r_Reset <= 1'b0;
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@(posedge r_Clk);
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r_Latch <= 1'b1;
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@(posedge r_Clk);
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r_Latch <= 1'b0;
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@(posedge r_Clk);
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r_Data <= 0;
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r_Latch <= 1'b1;
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@(posedge r_Clk);
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r_Latch <= 1'b0;
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@(posedge r_Clk);
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r_Latch <= 1'b1;
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@(posedge r_Clk);
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r_Latch <= 1'b0;
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@(posedge r_Clk);
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r_Data <= 1;
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r_Latch <= 1'b1;
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@(posedge r_Clk);
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r_Latch <= 1'b0;
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@(posedge r_Clk);
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#5;
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$finish();
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end
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endmodule
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