45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
module Binary_to_7_Segment(
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input i_Clk,
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input [$clog2(15)-1:0] i_Number,
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output o_SegA,
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output o_SegB,
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output o_SegC,
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output o_SegD,
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output o_SegE,
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output o_SegF,
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output o_SegG
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);
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reg [6:0] r_HexEncoding;
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always @(posedge i_Clk) begin
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case (i_Number)
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0: r_HexEncoding <= 7'b1111110;
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1: r_HexEncoding <= 7'b0110000;
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2: r_HexEncoding <= 7'b1101101;
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3: r_HexEncoding <= 7'b1111001;
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4: r_HexEncoding <= 7'b0110011;
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5: r_HexEncoding <= 7'b1011011;
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6: r_HexEncoding <= 7'b1011111;
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7: r_HexEncoding <= 7'b1110000;
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8: r_HexEncoding <= 7'b1111111;
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9: r_HexEncoding <= 7'b1111011;
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10: r_HexEncoding <= 7'b1110111;
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11: r_HexEncoding <= 7'b0011111;
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12: r_HexEncoding <= 7'b1001110;
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13: r_HexEncoding <= 7'b0111101;
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14: r_HexEncoding <= 7'b1001111;
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15: r_HexEncoding <= 7'b1000111;
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default: r_HexEncoding <= 7'b0000000;
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endcase
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end
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assign o_SegA = r_HexEncoding[6];
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assign o_SegB = r_HexEncoding[5];
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assign o_SegC = r_HexEncoding[4];
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assign o_SegD = r_HexEncoding[3];
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assign o_SegE = r_HexEncoding[2];
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assign o_SegF = r_HexEncoding[1];
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assign o_SegG = r_HexEncoding[0];
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endmodule
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