82 lines
1.7 KiB
Verilog
82 lines
1.7 KiB
Verilog
module VGAImageRenderer(
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input i_Clk,
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input i_HSync,
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input i_VSync,
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output o_HSync,
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output o_VSync,
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output [2:0] o_Red,
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output [2:0] o_Green,
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output [2:0] o_Blue
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);
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// sync signals
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wire w_HSync_FromCurrentPos, w_VSync_FromCurrentPos;
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wire w_IsActiveArea;
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// screen location
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wire [9:0] w_X, w_Y;
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wire [6:0] w_CellX;
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wire [5:0] w_CellY;
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// ram reading
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reg r_doImageRAMRead = 1;
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reg r_doImageRAMWrite = 0;
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wire w_imageRAMReadDataReady;
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wire [4:0] w_imageRAMReadData;
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wire [2:0] w_Red, w_Green, w_Blue;
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VGA_Current_Beam_Position currentPos (
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.i_Clk(i_Clk),
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.i_HSync(i_HSync),
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.i_VSync(i_VSync),
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.o_HSync(w_HSync_FromCurrentPos),
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.o_VSync(w_VSync_FromCurrentPos),
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.o_X(w_X),
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.o_Y(w_Y),
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.o_IsActiveArea(w_IsActiveArea)
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);
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assign w_CellX = w_X[9:3];
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assign w_CellY = w_Y[9:3];
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// takes a tick, so add one to HSync/VSync
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ImageRAM imageRam (
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.i_Clk(i_Clk),
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.i_ReadX(w_CellX),
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.i_ReadY(w_CellY),
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.i_doRead(r_doImageRAMRead),
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.o_ReadDataReady(w_imageRAMReadDataReady),
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.o_ReadData(w_imageRAMReadData),
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.i_WriteX(),
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.i_WriteY(),
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.i_WriteData(),
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.i_DoWrite(r_doImageRAMWrite),
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.o_WriteComplete()
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);
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ImageIndexToColor palette (
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.i_Clk(i_Clk),
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.i_ColorIndex(w_imageRAMReadData),
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.o_Red(w_Red),
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.o_Green(w_Green),
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.o_Blue(w_Blue),
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.i_DoWrite(r_doImageRAMWrite),
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.i_WriteColorIndex(),
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.i_WriteColor_Red(),
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.i_WriteColor_Green(),
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.i_WriteColor_Blue(),
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.o_WriteComplete()
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);
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assign o_Red = w_IsActiveArea ? w_Red : 0;
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assign o_Green = w_IsActiveArea ? w_Green : 0;
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assign o_Blue = w_IsActiveArea ? w_Blue : 0;
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assign o_HSync = w_HSync_FromCurrentPos;
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assign o_VSync = w_VSync_FromCurrentPos;
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endmodule
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