104 lines
2.6 KiB
Verilog
104 lines
2.6 KiB
Verilog
/**
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* The output is buffered as the front/back porches are added, so watch your
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* timing for other stuff.
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*
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* Side effects:
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* * Blanks o_<color> if within HSync/VSync
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*/
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module VGA_Add_Porches_To_Output(
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input i_Clk,
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input i_HSync,
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input i_VSync,
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input [VIDEO_WIDTH-1:0] i_Red,
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input [VIDEO_WIDTH-1:0] i_Green,
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input [VIDEO_WIDTH-1:0] i_Blue,
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output reg o_HSync,
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output reg o_VSync,
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output reg [VIDEO_WIDTH-1:0] o_Red,
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output reg [VIDEO_WIDTH-1:0] o_Green,
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output reg [VIDEO_WIDTH-1:0] o_Blue
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);
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parameter VIDEO_WIDTH = 3;
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parameter TOTAL_COLUMNS = 800;
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parameter TOTAL_ROWS = 525;
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parameter ACTIVE_COLUMNS = 640;
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parameter ACTIVE_ROWS = 480;
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//parameter FRONT_PORCH_COUNT_X = 18;
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parameter FRONT_PORCH_COUNT_X = 15;
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//parameter FRONT_PORCH_COUNT_Y = 10;
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parameter FRONT_PORCH_COUNT_Y = 10;
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//parameter BACK_PORCH_COUNT_X = 50;
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parameter BACK_PORCH_COUNT_X = 53;
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//parameter BACK_PORCH_COUNT_Y = 33;
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parameter BACK_PORCH_COUNT_Y = 33;
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wire w_HSync, w_VSync;
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wire [$clog2(TOTAL_COLUMNS)-1:0] w_X;
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wire [$clog2(TOTAL_ROWS)-1:0] w_Y;
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reg [VIDEO_WIDTH-1:0] r_Red = 0;
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reg [VIDEO_WIDTH-1:0] r_Green = 0;
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reg [VIDEO_WIDTH-1:0] r_Blue = 0;
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VGA_Current_Beam_Position #(
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.TOTAL_COLUMNS(TOTAL_COLUMNS),
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.TOTAL_ROWS(TOTAL_ROWS)
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) CurrentPosition (
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.i_Clk(i_Clk),
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.i_HSync(i_HSync),
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.i_VSync(i_VSync),
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.o_HSync(w_HSync),
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.o_VSync(w_VSync),
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.o_X(w_X),
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.o_Y(w_Y)
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);
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wire w_withinHPorch, w_withinVPorch, w_withinSync;
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assign w_withinHPorch = (w_X < FRONT_PORCH_COUNT_X + ACTIVE_COLUMNS) ||
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(w_X > TOTAL_COLUMNS - BACK_PORCH_COUNT_X - 1);
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assign w_withinVPorch = (w_Y < FRONT_PORCH_COUNT_Y + ACTIVE_ROWS) ||
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(w_Y > TOTAL_ROWS - BACK_PORCH_COUNT_Y - 1);
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assign w_withinSync = (w_X > ACTIVE_COLUMNS) || (w_Y > ACTIVE_COLUMNS);
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// https://web.mit.edu/6.111/www/s2004/NEWKIT/vga.shtml
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always @(posedge i_Clk) begin
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if (w_withinHPorch) begin
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o_HSync <= 1;
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end else begin
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o_HSync <= w_HSync;
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end
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if (w_withinVPorch) begin
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o_VSync <= 1;
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end else begin
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o_VSync <= w_VSync;
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end
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end
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// The process of going through Current Beam Position and then
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// the porch alignment above delays the video signal by two clock ticks.
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// Do the same input -> wire -> output as above.
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always @(posedge i_Clk) begin
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r_Red <= i_Red;
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r_Green <= i_Green;
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r_Blue <= i_Blue;
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// Ensure we never deliver color data during hsync/vsync
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if (w_withinSync) begin
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o_Red <= 0;
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o_Green <= 0;
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o_Blue <= 0;
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end else begin
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o_Red <= r_Red;
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o_Green <= r_Green;
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o_Blue <= r_Blue;
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end
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end
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endmodule
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