99 lines
2.3 KiB
Verilog
99 lines
2.3 KiB
Verilog
module UART_TX (
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input i_Reset_Low,
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input i_Clk,
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input i_TransmitReady,
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input [7:0] i_TransmitByte,
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output reg o_Active,
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output reg o_Output,
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output reg o_Done
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);
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parameter CLOCKS_PER_SECOND = 25000000;
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parameter BAUD_RATE = 115200;
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localparam integer CLOCKS_PER_BIT = CLOCKS_PER_SECOND / BAUD_RATE;
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localparam IDLE = 0;
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localparam SEND_START_BIT = 1;
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localparam SEND_DATA_BITS = 2;
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localparam SEND_STOP_BIT = 3;
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reg [$clog2(SEND_STOP_BIT)-1:0] r_currentState = IDLE;
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reg [$clog2(CLOCKS_PER_BIT)-1:0] r_clockCount = 0;
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reg [$clog2(8)-1:0] r_bitIndex = 0;
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reg [7:0] r_transmitData;
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always @(posedge i_Clk or negedge i_Reset_Low) begin
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if (!i_Reset_Low) begin
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r_currentState <= IDLE;
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end else begin
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o_Done <= 0;
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case (r_currentState)
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IDLE:
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begin
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// Drive line high for idle
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o_Output <= 1;
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r_clockCount <= 0;
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r_bitIndex <= 0;
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if (i_TransmitReady) begin
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o_Active <= 1;
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r_transmitData <= i_TransmitByte;
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r_currentState <= SEND_START_BIT;
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end
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end
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SEND_START_BIT:
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begin
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o_Output <= 0;
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if (r_clockCount < CLOCKS_PER_BIT - 1) begin
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r_clockCount <= r_clockCount + 1;
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end else begin
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r_clockCount <= 0;
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r_currentState <= SEND_DATA_BITS;
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end
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end
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SEND_DATA_BITS:
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begin
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o_Output <= r_transmitData[r_bitIndex];
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if (r_clockCount < CLOCKS_PER_BIT - 1) begin
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r_clockCount <= r_clockCount + 1;
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end else begin
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r_clockCount <= 0;
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if (r_bitIndex == 7) begin
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r_bitIndex <= 0;
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r_currentState <= SEND_STOP_BIT;
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end else begin
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r_bitIndex <= r_bitIndex + 1;
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end
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end
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end
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SEND_STOP_BIT:
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begin
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o_Output <= 1;
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if (r_clockCount < CLOCKS_PER_BIT - 1) begin
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r_clockCount <= r_clockCount + 1;
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end else begin
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o_Done <= 1;
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r_clockCount <= 0;
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r_currentState <= IDLE;
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o_Output <= 0;
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end
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end
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default:
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begin
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r_currentState <= IDLE;
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end
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endcase
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end
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end
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endmodule
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