15 lines
337 B
Verilog
15 lines
337 B
Verilog
module Demux_1_to_4(
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input i_Data,
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input i_Sel0,
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input i_Sel1,
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output o_Data0,
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output o_Data1,
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output o_Data2,
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output o_Data3
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);
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assign o_Data0 = i_Data & !i_Sel0 & !i_Sel1;
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assign o_Data1 = i_Data & i_Sel0 & !i_Sel1;
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assign o_Data2 = i_Data & !i_Sel0 & i_Sel1;
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assign o_Data3 = i_Data & i_Sel0 & i_Sel1;
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endmodule
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