module RAM(
  input i_writeClock,
  input [$clog2(DEPTH_WORDS - 1):0] i_writeAddress,
  input [WIDTH_BITS-1:0] i_writeData,
  input i_writeDataValid,

  input i_readClock,
  input [$clog2(DEPTH_WORDS - 1):0] i_readAddress,
  input i_doRead,
  output reg o_dataValid,
  output reg [WIDTH_BITS-1:0] o_readData
);
  parameter WIDTH_BITS = 8;
  parameter DEPTH_WORDS = 16;

  reg [WIDTH_BITS-1:0] r_Memory[DEPTH_WORDS-1:0];

  always @(posedge i_writeClock) begin
    if (i_writeDataValid) begin
      r_Memory[i_writeAddress] <= i_writeData;
    end
  end

  always @(posedge i_readClock) begin
    o_readData <= r_Memory[i_readAddress];
    o_dataValid <= i_doRead;
  end
endmodule

module TestRAM();
  reg r_Clk = 0;

  always #2 r_Clk <= !r_Clk;

  reg [4:0] r_writeAddress = 1;
  reg [7:0] r_writeData = 50;
  reg r_writeDataValid = 0;

  reg [4:0] r_readAddress = 1;
  wire [7:0] w_readData;
  reg r_doRead = 0;
  wire w_dataValid;

  RAM myRam (
    .i_writeClock(r_Clk),
    .i_writeAddress(r_writeAddress),
    .i_writeData(r_writeData),
    .i_writeDataValid(r_writeDataValid),

    .i_readClock(r_Clk),
    .i_readAddress(r_readAddress),
    .i_doRead(r_doRead),
    .o_dataValid(w_dataValid),
    .o_readData(w_readData)
  );

  initial begin
    $dumpfile("test.vcd");
    $dumpvars;

    #2;

    r_writeDataValid <= 1;

    #2;

    r_writeDataValid <= 0;

    #2;

    r_doRead <= 1;

    #2;

    $finish;
  end
endmodule