29 lines
1.3 KiB
Markdown
29 lines
1.3 KiB
Markdown
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# Go Board code reworking
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This code is a reworking of the code for the [Go Board](https://nandland.com/the-go-board/)
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FPGA beginner's board.
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The original code comes from two sources:
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* [Nandland Go Board tutorials](https://nandland.com/download-and-install-the-fpga-tools-and-drivers/)
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* [Getting Started with FPGAs repo](https://github.com/nandland/getting-started-with-fpgas/)
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Where possible I tried to:
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* use more consistent variable and constant names
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* fix missing inferred wires (the Pong project had a lot of these)
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* avoid run-on lines of code
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* avoid one-liner conditional bodies, opting for `begin...end` blocks everywhere
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All of these can be built with [Yosys](https://github.com/YosysHQ/yosys)
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and tested with [Icarus Verilog](https://github.com/steveicarus/iverilog). The `Makefile` is one I've been dragging along across all projects. It can fire off both a build-and-install to the Go Board, as well as run the test suite and open up [GTKWave](https://gtkwave.sourceforge.net/)
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so you can inspect the signals. You do not need Lattive iCECube2 and you will have a hard time
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getting it to run on modern Linux anyway!
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`sipo_shift_register_test.sv` shows how to create your own `assert` for Icarus Verilog,
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taken from an idea from here: https://stackoverflow.com/a/13906120
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Have fun.
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John
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